Piconet registers 00-1Fh
This article may be updated if/when I fill in gaps from the ROM disassembly- it's not yet a complete description of the functionality.
The manual (RM PN 15283) for the Piconet parallel interface module identifies 00-1Fh as "Common Piconet registers", and doesn't go into detail about them. Here's what I could determine about those registers from disassembling the module's ROM (and a few from the RM Nimbus Museum).
| Address | R/W | Function |
| 00h | R/O | Status |
| 01h | R/W | Piconet module type MSB (probably 00h) |
| 02h | R/W | Piconet module type LSB (01h=serial, 02h=parallel) |
| 03h | R/W | Piconet address |
| 04h | R/O | ? (returns 01h) |
| 05h | R/W | EEROM address |
| 06h | R/W | EEROM read |
| 07h | R/W | EEROM buffer pointer |
| 08h | - | No-op (return address * 2, ie 10h) |
| 09h | R/W | 8031 register P0 |
| 0Ah | R/W | 8031 register P1 |
| 0Bh | R/W | 8031 register P2 |
| 0Ch | R/W | 8031 register P3 |
| 0Dh | R/W | 8031 register TMOD |
| 0Eh | R/W | 8031 register TCON |
| 0Fh | R/W | 8031 register TH0 |
| 10h | R/W | 8031 register TL0 |
| 11h | R/W | 8031 register TH1 |
| 12h | R/W | 8031 register TL1 |
| 13h | R/W | 8031 register SCON |
| 14h | R/W | 8031 register SBUF |
| 15h | R/W | 8031 register PCON |
| 16h | R/W | ? RAM_62 |
| 17h | R/O | ROM minor version |
| 18h | R/O | ROM major version |
| 19h | R/O | ROM version suffix |
| 1Ah | - | No-op (return address * 2) |
| 1Bh | - | No-op (return address * 2) |
| 1Ch | - | No-op (return address * 2) |
| 1Dh | - | No-op (return address * 2) |
| 1Eh | - | No-op (return address * 2) |
| 1Fh | - | No-op (return address * 2) |
00h - Status
Read: Status bitfield as follows
- Timeout (set by reaching the timeout, as set in register 35h on the parallel module, cleared before any request that isn't a type 0 status request)
- EEROM operation pending
- Not used, on the parallel module at least
- Bad request (set by a request to an invalid register or with invalid request type, cleared by the next valid register read/write)
- Error (set by various errors specific to the module, cleared on the parallel module by reading register 26h)
- Probably not used (the only instruction that sets it appears to be always skipped over), on the parallel module at least
- Transmit buffer is full
- Receive buffer contains data
01h - Piconet module type MSB
Write: to 8031 internal RAM, address 5Dh
Read: Nimbus Museum identifies this as an "are you there?" check. From the code it looks like an MSB corresponding to an LSB given by register 02h. Returns 00h on their serial module and my parallel module.
02h - Piconet module type LSB
Write: to 8031 internal RAM, address 5Eh
Read: Piconet module type- 01h for a serial module, 02h for a parallel module
03h - Piconet address
Write: Set this module's Piconet address. If an address greater than 30 is given, 30 will be set. If an address less than 1 is given, 1 will be set.
Read: Get this module's current Piconet address (which you may well already know, if you just addressed the module to try to read it)
04h
Read: Returns a hard-coded 01h on my parallel module, but I'm not sure what this represents.
05h - EEROM address
Write: to 8031 internal RAM, address 5Fh (and a couple of bits in 20-21h)
Read: from the same location
06h - EEROM read
Write: to 8031 internal RAM, address 60h
Read: Causes a word to be read from the EEROM. The address in the EEROM is passed in register 05h. The MSB of the word is placed in RAM pointed to by register 07h; the LSB is placed directly below it.
07h - EEROM buffer pointer
Write: to 8031 internal RAM, address 61h (and a couple of bits in 20-21h)
Read: from the same location
08h - No-op
Code does nothing here. Read byte will be the register number times 2, being an offset into a jump table. (Same as 1A-1Fh)
09h - P0
Direct read/write access to 8031 register P0 (port 0 GPIOs)
0Ah - P1
Direct read/write access to 8031 register P1 (port 1 GPIOs)
0Bh - P2
Direct read/write access to 8031 register P2 (port 2 GPIOs)
0Ch - P3
Direct read/write access to 8031 register P3 (port 3 GPIOs)
0Dh - TMOD
Direct read/write access to 8031 register TMOD (timer mode)
0Eh - TCON
Direct read/write access to 8031 register TCON (timer 0/1 control)
0Fh - TH0
Direct read/write access to 8031 register TH0 (timer 0 high byte)
10h - TL0
Direct read/write access to 8031 register TL0 (timer 0 low byte)
11h - TH1
Direct read/write access to 8031 register TH1 (timer 1 high byte)
12h - TL1
Direct read/write access to 8031 register TL1 (timer 1 low byte)
13h - SCON
Direct read/write access to 8031 register SCON (serial control)
14h - SBUF
Direct read/write access to 8031 register SBUF (serial buffer)
15h - PCON
Direct read/write access to 8031 register PCON (power control)
16h
Write: to 8031 internal RAM, address 62h (and a couple of bits in 21-22h)
Read: 00h if bit 3 at RAM address 21h is clear, FFh if set
17h - ROM minor version
Read: Minor part of the ROM version number, according to Nimbus Museum. 01h on their serial and my parallel module.
18h - ROM major version
Read: Major part of the ROM version number, according to Nimbus Museum. 01h on their serial and my parallel module.
19h - ROM version suffix
Read: Letter suffix of the ROM version number, according to Nimbus Museum. ASCII A on their serial module, B on my parallel module.
1A-1Fh - No-op
Code does nothing here. Read byte will be the register number times 2, being an offset into a jump table. (Same as 08h)
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